Manisha Guduri ¹, Aminul Islam ¹

Affiliations
1 Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi - 835215, Jharkhand, IN

Abstract

Objectives: This paper analyses various Complementary MOS (CMOS) based XOR circuits in terms of their output voltage levels at deep subthreshold/low frequency region at 16-nm technology node and finds out the suitable XOR circuit for ultralow-power applications. Methods/Analysis: It also provides the worst case high and low output level for various XOR circuits at supply voltage 130 mV. Findings: In addition, it compares the average power dissipation that is the sum of both dynamic and leakage power dissipation (stand-by power dissipation) of XOR circuits along with the variability analysis of power dissipation in order to find the XOR circuit which is most robust and dissipate the least average power. Novelty/Improvement: Simulation result shows that Power-less XOR circuit is having a good output high and low level in all cases and most promising in terms of robustness and average power dissipation among all the other XOR circuits at deep subthreshold/ low frequency region of operation.

Keywords

Average Power Dissipation, CMOS, Low Frequency, Subthreshold Region.

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Manisha Guduri ¹, Amit Krishna Dwivedi ¹, Aminul Islam ¹

Affiliations
1 Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi - 835215, Jharkhand, IN

Abstract

Objectives: The objective of this research paper is to design High Vt-Low Leakage FDSOI Device for Ultra-Low Power Operation. Methods/Analysis: This research work presents the modeling of fully depleted silicon on insulator (FDSOI) device with 350-nm gate length. This paper investigates threshold voltage (Vt) and leakage power of the different FDSOI devices in order to design high threshold voltage and low leakage device. Findings: It is observed that device5 shows higher Vt and dissipates lower leakage power when compared to that of other devices (devices1−4). The threshold voltage and subthreshold slope (SS) of device5 are observed to be 0.199 V (~0.2 V) and 80 mV/decade respectively. The leakage power of the device at drain voltage of 1 V is 41.9 nW. Novelty /Improvement: This kind of FDSOI device is a platform for designing circuits at nano scale regime for ultra-low power applications.

Keywords

FDSOI Device, Leakage Power, Threshold Voltage, Subthreshold Slope

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